The present invention relates generally to semiconductor devices and more particularly to apparatus and methods for generating a reference voltage to sense data stored in memory devices.
Ferroelectric memory devices, and other type semiconductor memories, are used for storing data and/or program code in personal computer systems, embedded processor-based systems, and the like. Ferroelectric memories are commonly organized in single-transistor, single-capacitor (1T1C) or two-transistor, two-capacitor (2T2C) configurations, in which data is read from or written to the device using address signals and various other control signals. The individual memory cells typically comprise one or more ferroelectric (FE) capacitors adapted to store a binary data bit, as well as one or more access transistors, typically MOS devices, operable to selectively connect the FE capacitor to one of a pair of complimentary bit lines, with the other bit line being connected to a reference voltage. The individual cells are commonly organized as individual bits of a corresponding data word, wherein the cells of a given word are accessed concurrently through activation of plate lines and word lines by address decoding circuitry.
Ferroelectric memory devices provide non-volatile data storage where data memory cells include capacitors constructed with ferroelectric dielectric material which may be polarized in one direction or another in order to store a binary value. The ferroelectric effect allows for the retention of a stable polarization in the absence of an applied electric field due to the alignment of internal dipoles within Perovskite crystals in the dielectric material. This alignment may be selectively achieved by application of an electric field to the ferroelectric capacitor in excess of the coercive field of the material. Conversely, reversal of the applied field reverses the internal dipoles. The response of the polarization of a ferroelectric capacitor to the applied voltage may be plotted as a hysteresis curve.
Data in a 1T1C type ferroelectric data cell is read by connecting a reference voltage to a first bit line and connecting the cell ferroelectric capacitor between a complimentary bit line and a plate line signal voltage, and interrogating the cell. There are several techniques to interrogate a FeRAM cell. Two most common interrogation techniques are on-pulse sensing and after-pulse sensing. In both these interrogation techniques, the cell capacitor is coupled to the complimentary bit line by turning ON an access or a pass gate. In the on-pulse sensing, the plate line voltage is stepped from ground (Vss) to a supply voltage (Vdd). In the after-pulse sensing the plate line voltage is pulsed from Vss to Vdd and then back to Vss. In either case, the application of the voltage to the plate line provides a differential voltage on the bit line pair, which is connected to a sense amp circuit. The reference voltage is typically supplied at an intermediate voltage between a voltage (Vxe2x80x9c0xe2x80x9d) associated with a capacitor programmed to a binary xe2x80x9c0xe2x80x9d and that of the capacitor programmed to a binary xe2x80x9c1xe2x80x9d (Vxe2x80x9c1xe2x80x9d). The resulting differential voltage at the sense amp terminals represents the data stored in the cell, which is buffered and applied to a pair of local IO lines.
The transfer of data between the ferroelectric memory cell, the sense amp circuit, and the local data bit lines is controlled by various access transistors, typically MOS devices, with switching signals being provided by control circuitry in the device. In a typical ferroelectric memory read sequence, two sense amp bit lines are initially pre-charged to ground, and then floated, after which a target ferroelectric memory cell is connected to one of the sense amp bit lines and interrogated. Thereafter, a reference voltage is connected to the remaining sense amp bit line, and a sense amp senses the differential voltage across the bit lines and latches a voltage indicative of whether the target cell was programmed to a binary xe2x80x9c0xe2x80x9d or to a xe2x80x9c1xe2x80x9d.
FIG. 1 schematically illustrates an exemplary, conventional segment portion of a memory device 2 having 512 rows (words) and 64 columns (bits) of data storage cells CROW-COLUMN configured in a folded bit line architecture, where each column of cells is accessed via a pair of complimentary bit lines BLCOLUMN and BLCOLUMNxe2x80x2. One exemplary column of the device 2 is illustrated in prior art FIG. 2. The cells C1-1 through C1-64 form a data word accessible via a word line WL1 and complimentary bit line pairs BL1/BL1xe2x80x2 through BL64/BL64xe2x80x2, where cell data is sensed during data read operations using sense amp circuits S/A Cl through S/A C64 associated with columns 1 through 64, respectively. In a typical folded bit line architecture ferroelectric memory device, the cells CROW-COLUMN individually include one or more ferroelectric cell capacitors and one or more access transistors to connect the cell capacitors between one of the complimentary bit lines associated with the cell column and a plate line, where the other bit line is connected to a reference voltage.
In the device 2, the sense amps associated with even numbered columns are located at the bottom of the segment, whereas sense amps associated with odd numbered columns are located at the top of the segment. Reference voltages are provided in a variety of differing manners. For example, in the example of prior art FIG. 1, to reduce the number of components in the device 2, as well as to increase device density therein, individual reference voltage generators are not provided for each complimentary bit line pair. Rather, shared reference generators are provided at the top and bottom of the segment columns. An even column reference generator 8 is provided at the bottom of the segment columns to service the sense amps associated with even numbered columns and an odd column reference generator 8xe2x80x2 is provided at the top of the segment columns to service the sense amps associated with odd numbered columns. The reference voltages from the generators 8, 8xe2x80x2 are coupled to one of the bit lines in the columns using one of a pair of switches 8a, Bb, depending upon whether an odd or even numbered target data word is being read.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
In accordance with one aspect of the invention, a logic programmable reference voltage circuit is provided for a ferroelectric memory. The logic programmable reference voltage circuit is operable to generate a reference voltage value that is variable, and is a function of one or more input control signals. For example, based on a sense technique selected used (e.g., after-pulse or on-pulse sensing), or a type of reference employed (e.g., Da or U), a different reference voltage value may be generated such that errors during a sense mode are substantially reduced.
In another aspect of the present invention, a ferroelectric memory is disclosed that comprises a reference control circuit, a logic programmable reference circuit and a memory block having a 1T1C type memory architecture. The reference control circuit is operable to generate one or more control signals in response to one or more input conditions, such as location data, thermal data, sense methodology data, test mode data, time, and the like. The logic programmable reference circuit receives the control signals from the reference control circuit and generates a capacitance value in response thereto. The capacitance is then coupled to the memory block and forms a capacitor divider with one or more bit lines associated with the block to generate a voltage reference having a value associated with the capacitance value.
In yet another aspect of the present invention, the logic programmable reference circuit comprises a variable capacitance circuit, wherein the variable capacitance circuit is operable to couple a number of capacitances together in parallel based on the control signals from the reference control circuit. The parallel capacitances together form the circuit capacitance that is coupled to the memory block to form the capacitor divider circuit.
In still another aspect of the present invention, the variable capacitance circuit comprises a plurality of capacitances that are weighted with respect to one another in a binary fashion. The capacitances are selectively coupled together in parallel by a plurality of switches that are controlled by the control signals of the reference control circuit. Based on the control signals, one or more of the plurality of switches are activated, thereby selectively coupling the capacitances associated with the activated switches together in parallel to form a collective capacitance for the variable capacitance circuit. One or more bit lines in the memory block are then coupled to the variable capacitance circuit, and the capacitance associated with the bit lines form a capacitor divider circuit with the collective capacitance to form a reference voltage.
In yet another aspect of the present invention, the capacitance in the variable capacitance circuit comprises ferroelectric capacitors that are identical to the ferroelectric capacitors employed in the memory block. The binary weighting in each of the legs of the variable capacitance circuit may be provided by coupling multiple ferroelectric capacitors together in parallel.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.